PIC16F59 LogicAnalyser
The PIC16F59, with it's 32 i/o pins can be used as a 'logic analyser' to monitor the operation other PIC's. The only drawback is lack of memory (it has only 134 registers) - so you either need to add an external 'store' or 'off-load' the data captured in more or less 'real time'
In practice, no more than 24 pins (3 sets of 8) will be available for 'capture' = the remaining 2 sets of 4 will be needed for control and data output.
Run at 20MHz, the 16F59 should be quite capable of monitoring the operation of the 'real time clock' (32kHz) PIC - and especially it's 'serial output' - as well as monitoring the inputs and outputs of the 'Star Tracking' PIC
A 20MHz clk with 4 CLK per CPU cycle gives us 5 MIPS (5 MHz). However, whilst it's possible to 'grab' the values of one set of PORT pins in one CPU instruction, the value then has to be 'saved'. A 'stack' of in-line 'sample' and 'save' instructions gives us a max. 'burst' speed of 2.5MHz - and this is limted to 16 bytes (due to the nature iof tghe 16F59 register 'bank' addressing system)
PC support
The need to 'off load' data in 'real time' leads to the use of a PC as a 'storage' device - the PIC16F59 sending it's captured data to the PC via the serial link
What's the max sustained capture speed ?
Grab a byte - 1 CLK, save it 1 CLK, transmit it (which takes at least 4 CLK's per bit), so 4x8 = 32 CLK's per byte. The max. speed plainly depends on how fast we can output the bits, for which we will use the I2C protocol.
I2C protocol
The 'I2C' protocol uses 2 lines, 1 for Clock (SLC) and the other for Data (SLD). To drive the I2C lines, the TRIS regsiter must be used (you must only drive the line 'Lo', so the PIC PORT data is set to '00' and TRIS used to 'turn on' = Lo (0), or leave the line tri-state = Hi (1).
To send data via I2C you proceed as follows :-
With the Clock 'Lo', set the value of the Data bot (b7 first, b0 last).
Set Clk Hi.
Set Clk Lo.
Change the Data to the next bit
Set Clk Hi.
Set Clk Lo.
Change the Data to the next bit
...
I2C has a very high 'overhead' - you have to transmit a destination 'register address' prior to each data byte (if you are addressing a 1Mbyte serial RAM chip, the 'destination' address will be 20 bits long !)
Note that I2C defines 4 speed 'classes' = standard 100kHz, full 400kHz, fast 1MHz and high 3.2Mhz, however all devices are free to operate at whatever (slower) speed they like (i.e. so long as they don't go any faster than the max. class supported by the destination device)
So whats the max I2C speed the 16F59 can manage ?
The 'problem' is that the only way to 'control' the port 'tri-state' is the "TRIS PORTx" instruction, which means "Copy Acc to Tri-State latch for PORTx". Since both Clock and Data 'Hi' requires we set TriState mode, we have to 'shift' the data bits into the Acc (so they can be used to control the TRIS). At least TRIS bit 1 sets TriState 'Hi'.
The 'good' thing about I2C is that we don't have to care about maintaining a constant speed - i.e we can bit test and jump all over the place so long as the data is stable when Clk is Hi
; I2C using PORT E (which consist of top 4 bits only)
; RE7 = SLD (must be top bit as b7 is Tx'd first), RE6 = SLC (actually, any other bit would do)
Load Acc,00 ; start by making sure it's 'all Lo'
Copy Acc,PORT E ; set data Lo
TRIS PORTE ; set clk Lo
; OK, ready to do a byte, we are gong to use the good old 'destructive read out' approach
BSET Cy ;
; do a byte, start with first bit
Copy DataReg,Acc ; get the data
Loop;
ROTL Acc,DataReg ; shift data ready for next time (note, this shifts Cy into b0)
BCLR Acc,b6 ; Clk must stay Lo
TRIS PORTE ; set the data
BSET Acc,b6 ; Rdy Clk Hi
TRIS PORTE ; send Clk
BCLR Acc,b6 ; Rdy clk Lo
TRIS PORTE ; send Lo
CLT Cy ; clear Cy (for next shift)
Copy DataReg,Acc ; get the (ready shifted) data
Skip Z ; skip if zero = all bits done
JMP Loop: ; keep looping
; OK all bits done, now get the ACK
....
The tx loop is 12 CPU instruction cycles per bit. If assume another 12 cycles to get the 'ACK' or send a 'start' / 'stop', then we have a 'bit rate of 5Mz/12 = 416k bps (of course this ignores the time taken to 'sample' the data from the 'logical analyser' PORT etc)
Is there any way to speed up the transmission ?
Using the 'bit shift a whole PORT' method, data could be 'output' at a rate of 1 CPU cycle per bit.